How to protect hardware designs (but not too much…)
Christian Pilato
Assistant Professor at DEIB - Politecnico di Milano
DEIB - NECSTLab Meeting Room (Building 20, basement floor)
February 21st, 2020
11.30 am
Contacts:
Marco Santambrogio
Research line:
System architectures
Abstract
The globalization of the electronics supply chain allows for the reduction of chip manufacturing costs but poses new security threats concerning the protection of the intellectual property. Logic locking is a well-known technique for thwarting reverse engineering of chip designs by inserting additional gates controlled by an extra key that is not known to the untrusted foundry. So, the designer has to trade-off the protection of the circuit and the area overhead to create secure chips while reducing silicon costs.In this talk, I will show that the problem is even more complex. I will present a high-level design method for logic locking that operates at RTL or during HLS, together with a design space exploration framework to evaluate the security metrics of alternative solutions.
This study shows that an excessive protection of a circuit design not only increases the area overhead but also may decrease its security.
The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.
Every week, the "NECST Friday Talk" invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the "Computing Systems".