Security and privacy are becoming one of the major concerns for data elaboration, also considering the increasing globalization of the electronic supply chain. Modern computing systems must include hardware support to provide a fast and efficient mean to guarantee that valuable information is not stolen, protecting not only the user data but also the semiconductor intellectual property. While many solutions exist for these problems, they are usually applied in the last stages of the chip design, often jeopardizing the previous optimizations. Addressing hardware security during high-level synthesis (HLS) is an interesting approach to design and integrate solutions at higher levels of abstraction, co-optimizing them with the rest of the design.
In this talk, I will present recent research on HLS extensions for integrating several security features, like information flow tracking, watermarking and obfuscation. I will also present the other face of the coin: how HLS tools can be effectively compromised to become powerful attack vectors. Finally, I will outline the open challenges for addressing hardware security during high-level design.

The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures. 

Every week, the "NECST Friday Talk" invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the "Computing Systems".

Christian Pilato is an Assistant Professor at Politecnico di Milano. He has a Ph.D. in Information Technology from Politecnico di Milano (2011). He was a Post-doc Research Scientist at Columbia University (2013-2016) and Università della Svizzera Italiana (2016-2018). His research interests include high-level synthesis, reconfigurable systems, and system-on-chip architectures, with emphasis on memory and security aspects. He delivers invited keynotes, talks, and tutorials on high-level synthesis and system-on-chip design (FPT, FPL, CASES). He served as program chair of IEEE EUC 2014. He serves on the several program committees of several conferences in the area of embedded systems, CAD, and reconfigurable architectures (FPL, DATE, CASES). He is a member of IEEE, ACM and HiPEAC.