Designing Energy Efficient RISC V System-on-Chips

Speakers:  Emilio Corigliano, Niccolò Nicolosi

April 30^th, 2026 | 10:00 am
DEIB, "Schiavoni" Room (Bld. 20A)

Contact: phd-inf@polimi.it

Abstract

On April 30^th, 2026, at 10:00 am Emilio Corigliano and Niccolò Nicolosi, PHD Students in Information Technology, will give a seminar on "Designing Energy Efficient RISC V System-on-Chips" in DEIB, "Schiavoni" Room (Building 20A).

In this seminar we will talk about the open-source RISC-V processors, focusing on their relation with energy consumption for energy-efficient edge applications. We will start with the basics of the RISC-V ISA, then show how standard and custom extensions let you match the processor design to the wanted workload. We will finally discuss tightly coupled co-processors that act as accelerators and we will briefly explore how these RISC-V building blocks can be used for implementing ASICs, CGRAs, embedded FPGAs, or in-memory computing fabrics.