As the technology node continuously scales down, Moore’s law may not be sustainable as before for conventional CMOS technology. To deal with this challenge, several emerging technologies have been proposed. Among them, 3D integration, spintronic and carbon nanotube technologies have their unique desirable merits, and are promising cadidates for next generation of logic and memory design. On the other hand, since these technologies are not very mature yet, it is imperative to enhance the reliability and the energy efficiency from both circuit level and architecture level perspectives to guarantee the commercial success of these emerging technologies. In this talk, I will introduce my group’s several relevant work on low power and reliability design of the emerging technologies mentioned above.

The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.

Dr. Cheng got his Ph.D. degree from Institute of Comupting Technology, Chinese Academy of Sciences in 2012. Then, he spent one year at CNRS/LIRMM laboratory, Montpellier, France. At the end of 2013, he joined EE department of Beihang University as an assistant professor. During 2015 – 2016, he went to University of California, Santa Barbara, U.S. as a visiting scholar. His research topic includes low power and reliability design for 3D integerated circuits, low power and reliability design for emerging memory technologies, especially STT-MRAM and carbon nanotube devices. He has co-authored more than 40 peer-reivewed papers. He is a member of IEEE/ACM/IEICE/SIGDA/CEDA, a member of IFIP Working Group 10.5, a senior member of CCF (China Computing Federation), and is the TPC member of IEEE/ACM DATE conference, IEEE/ACM ISQED conference, IEEE PATMOS conference and IEEE ISVLSI conference.