The project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010.
The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node.
Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance).
The project will cover material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Starting on Jan 2008.