The RISC-V Vector Extension: Architecture, Flexibility, and Performance Trade-offs

23 Ottobre 2026 | 10:15
DEIB, Aula 1A (Ed. 20)

Contatti: phd-inf@polimi.it

Sommario

On October 23^rd, 2026, at 10:15 am Adriano Guarisco, PHD Student in Information Technology, will give a seminar on "The RISC-V Vector Extension: Architecture, Flexibility, and Performance Trade-offs" in DEIB, 1A Room (Building 20).

The RISC-V Vector Extension (RVV) provides a flexible and scalable approach to data-level parallelism.
This seminar will introduce the fundamental principles of vector computing and RVV, focusing on its vector-length-agnostic programming model and configurable vector operations. Particular emphasis will be given to trade-offs between instruction flexibility and their implementation complexity and execution overhead. Notable examples, such as strided or indexed memory accesses, masking, and vector reductions, will be considered to showcase how complex computation and memory access patterns can affect execution efficiency.
The seminar will also discuss the factors affecting vectorization effectiveness, including vector length utilization, instruction mix, and memory access patterns. Finally, the RISC-V Analyzer of Vector Executions (RAVE) will be briefly introduced as a tool for analyzing vectorized applications, identifying inefficiencies, and guiding software optimization.