Andrea Franchini received his Bachelor's Degree in Computer Engineering in 2020, and later his Master's Degree in Computer Science and Engineering in 2023 at Politecnico di Milano, with the thesis: "Verification and Synthesis of Infrastructure-as-Code through Satisfiability Modulo Theories". He continued his work as a Research Fellow on the EU-funded PIACERE project (https://piacere-project.eu), a DevSecOps framework, maintaining its Model Checker tool. His research focuses on synthesis of IaC via SMT solvers.