Towards full automation of the analog integrated circuits layout design process
Sommario
On July 21st, 2025 at 11.00 am Giuseppe Chiari, PHD Student in Information Technology, will hold a seminar on "Towards full automation of the analog integrated circuits layout design process" at DEIB 2A Room (Building 20).
Analog integrated circuits (ICs) play a vital role in a broad spectrum of modern electronic systems, including telecommunications, power electronics, audio processing, biomedical devices, and precision instrumentation. As demand grows for higher performance and increasingly compact analog ICs (especially in emerging domains such as edge systems) the complexity of their design becomes more pronounced. Unlike their digital counterparts, analog IC design remains predominantly manual, due to the tight coupling between circuit topology, layout-dependent parasitics, and performance metrics. This seminar addresses the ongoing challenge of analog layout design automation by presenting strategies and frameworks aimed at streamlining this process. We will delve into multi-stage pipelines that incorporate a mix of traditional design methodologies and novel AI-driven techniques to automate layout generation, validation, and optimization. Emphasis will be placed on recent advances in hardware-software co-design that facilitate faster, constraint-aware analog IC development, ultimately reducing time-to-market without compromising reliability or performance.
Analog integrated circuits (ICs) play a vital role in a broad spectrum of modern electronic systems, including telecommunications, power electronics, audio processing, biomedical devices, and precision instrumentation. As demand grows for higher performance and increasingly compact analog ICs (especially in emerging domains such as edge systems) the complexity of their design becomes more pronounced. Unlike their digital counterparts, analog IC design remains predominantly manual, due to the tight coupling between circuit topology, layout-dependent parasitics, and performance metrics. This seminar addresses the ongoing challenge of analog layout design automation by presenting strategies and frameworks aimed at streamlining this process. We will delve into multi-stage pipelines that incorporate a mix of traditional design methodologies and novel AI-driven techniques to automate layout generation, validation, and optimization. Emphasis will be placed on recent advances in hardware-software co-design that facilitate faster, constraint-aware analog IC development, ultimately reducing time-to-market without compromising reliability or performance.
