As the demand for efficient AI processing continues to grow, conventional hardware architectures struggle to meet the energy and latency constraints of modern deep learning applications, especially at the edge. This talk explores the critical role of hardware accelerators in overcoming these limitations, focusing on the synergy between open-source RISC-V architectures and emerging In-Memory Computing (IMC) paradigms.

 

The speech will begin by outlining the fundamental challenges in AI hardware design and the motivations for integrating IMC units. Then, Tommaso will present his recent research project: Extending the RISC-V Vector Instruction Set Architecture to Integrate Digital In-Memory Computing for Deep Learning Acceleration at the Edge. This work introduces custom instructions and a novel hardware-software co-design approach to seamlessly incorporate IMC into a vector processor, enabling higher throughput and energy efficiency for convolutional neural networks.

 

In the final part, the vision for the next phase of this research will be discussed: developing a modular and scalable architecture capable of bridging edge and high-performance computing (HPC) domains. This approach aims to unify flexibility, efficiency, and performance across the full spectrum of AI workloads.