NECSTFridayTalk – YoseUe: "Trimming" Random Forest's training towards resource-constrained inference
NECSTFridayTalk
Speaker: Alessandro Verosimile
DEIB PhD student
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
April 19th, 2024 | 11.30 am
Contact: Marco Santambrogio
Research Line: System architectures
Speaker: Alessandro Verosimile
DEIB PhD student
DEIB - NECSTLab Meeting Room (Bld. 20)
Online by Zoom
April 19th, 2024 | 11.30 am
Contact: Marco Santambrogio
Research Line: System architectures
Sommario
On April 19th, 2024 at 11.30 am a new appointment of NECSTFridayTalk series titled: "YoseUe: "Trimming. Random Forest's training towards resource-constrained inference" will take place at DEIB NECSTLab Meeting Room (Building 20) and on line by Zoom.
During this talk, we will have, as speaker Alessandro Verosimile, PhD student in Information Technology at DEIB, Politecnico di Milano on the following about the talk:
Endowing artificial objects with intelligence is a longstanding computer science and engineering vision that recently converged under the umbrella of Artificial Intelligence of Things (AIoT). Nevertheless, AIoT’s mission cannot be fulfilled if objects rely on the cloud for their “brain”. Thanks to heterogeneous hardware, it is possible to bring Machine Learning inference on resource-constrained embedded devices, but this requires careful co-optimization between model training and its hardware acceleration. This work proposes YoseUe, a memory-centric hardware co-processor for Random Forests inference, which significantly reduces the waste of memory resources by exploiting a novel train-acceleration co-optimization. YoseUe proposes a novel ML model, the Multi-Depth Random Forest Classifier (MDRFC), in which a set of RFs are trained at decreasing depths and then weighted, exploiting a Neural Network (NN) tailored to counteract potential accuracy losses w.r.t. classical RFs. Lastly, the proposed co-processor has been optimized by re-implementing it through SATL, a SoA spatial template to implement accelerators for irregular workloads. With the proposed approach it becomes possible to accelerate the inference of RFs that count up to 3 orders of magnitude more Decision Trees (DTs) than those the current state-of-the-art architectures can fit on embedded devices. Furthermore, this is achieved without losing accuracy with respect to classical, full-depth RF in their most relevant configurations.
During this talk, we will have, as speaker Alessandro Verosimile, PhD student in Information Technology at DEIB, Politecnico di Milano on the following about the talk:
Endowing artificial objects with intelligence is a longstanding computer science and engineering vision that recently converged under the umbrella of Artificial Intelligence of Things (AIoT). Nevertheless, AIoT’s mission cannot be fulfilled if objects rely on the cloud for their “brain”. Thanks to heterogeneous hardware, it is possible to bring Machine Learning inference on resource-constrained embedded devices, but this requires careful co-optimization between model training and its hardware acceleration. This work proposes YoseUe, a memory-centric hardware co-processor for Random Forests inference, which significantly reduces the waste of memory resources by exploiting a novel train-acceleration co-optimization. YoseUe proposes a novel ML model, the Multi-Depth Random Forest Classifier (MDRFC), in which a set of RFs are trained at decreasing depths and then weighted, exploiting a Neural Network (NN) tailored to counteract potential accuracy losses w.r.t. classical RFs. Lastly, the proposed co-processor has been optimized by re-implementing it through SATL, a SoA spatial template to implement accelerators for irregular workloads. With the proposed approach it becomes possible to accelerate the inference of RFs that count up to 3 orders of magnitude more Decision Trees (DTs) than those the current state-of-the-art architectures can fit on embedded devices. Furthermore, this is achieved without losing accuracy with respect to classical, full-depth RF in their most relevant configurations.
The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.
Every week, the “NECSTFridayTalk” invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the “Computing Systems”.
