Features Analysis of Microarchitectural Attacks and Hardware Trojan Horses in Microprocessors: Detection & Mitigation Techniques
Alessandro Palumbo
PhD student, Tor Vergata University - Rome
DEIB - BIO1 Room (Building 21, second floor)
July 6th, 2022
11.30 am
Contacts:
Daniele Ielmini
Research Line:
Electron devices
PhD student, Tor Vergata University - Rome
DEIB - BIO1 Room (Building 21, second floor)
July 6th, 2022
11.30 am
Contacts:
Daniele Ielmini
Research Line:
Electron devices
Sommario
On July 6th, 2022 at 11.30 am Alessandro Palumbo, PhD student at Tor Vergata University of Rome, will give a seminar on "Features Analysis of Microarchitectural Attacks and Hardware Trojan Horses in Microprocessors: Detection & Mitigation Techniques" in DEIB - BIO1 Room.
The continuous quest for performance pushed processors to incorporate elements like multiple cores, caches, acceleration units or speculative execution that make systems very complex and often expose unexpected vulnerabilities that pose new challenges.
For example, the timing differences introduced by caches or speculative execution can be exploited to leak information or detect activity patterns. Protecting modern microprocessors from attacks is extremely challenging and it is made even harder by the continuous rise of new microarchitectural attacks (e.g., the Rowhammer , Spectre, Meltdown attacks).
In addition, it has been demonstrated that Software exploitable Hardware Trojan Horses can be inserted in commercial CPUs and memories. Such attacks allow malicious users to run their own software or to gain unauthorized privileges over the system. The talk will present two methodologies for guarantee the security of microprocessor without modifying the CPU: the first one consists in implementing probabilistic data structures for monitoring the microprocessor fetching activity; the other is based on Machine Learning computations on some microprocessors features.
The continuous quest for performance pushed processors to incorporate elements like multiple cores, caches, acceleration units or speculative execution that make systems very complex and often expose unexpected vulnerabilities that pose new challenges.
For example, the timing differences introduced by caches or speculative execution can be exploited to leak information or detect activity patterns. Protecting modern microprocessors from attacks is extremely challenging and it is made even harder by the continuous rise of new microarchitectural attacks (e.g., the Rowhammer , Spectre, Meltdown attacks).
In addition, it has been demonstrated that Software exploitable Hardware Trojan Horses can be inserted in commercial CPUs and memories. Such attacks allow malicious users to run their own software or to gain unauthorized privileges over the system. The talk will present two methodologies for guarantee the security of microprocessor without modifying the CPU: the first one consists in implementing probabilistic data structures for monitoring the microprocessor fetching activity; the other is based on Machine Learning computations on some microprocessors features.
Biografia
Alessandro Palumbo is a PhD student of the University of Rome Tor Vergata in Electronics Engineering. He was a researcher assistant for the CNIT (Consorzio Nazionale Interuniversitario per le Telecomunicazioni), since April 2018 to October 2019.
He participated to two EU projects: SESAMO and 5G-PICTURE. He took master’s degree in Electronics Engineering for Telecommunications and Multimedia at the University of Tor Vergata in October 2019 and in the same University he took bachelor’s degree in Electronics Engineering in 2016. His research interests include hardware acceleration of networking functions and CPU microarchitectures, with particular emphasis on Machine Learning techniques and Probabilistic data structures for attacks detection.
