NECSTFridayTalk – Large forests and where to 'Partially' Fit Them
NECSTFridayTalk
Andrea Damiani
DEIB PhD student
Event will be online from Facebook
January 28th, 2022
1.00 pm
Contacts:
Marco Santambrogio
Research Line:
System architectures
Andrea Damiani
DEIB PhD student
Event will be online from Facebook
January 28th, 2022
1.00 pm
Contacts:
Marco Santambrogio
Research Line:
System architectures
Sommario
On January 28th, 2022 at 1.00 pm a new appointment of NECSTFridayTalk will be held online via Facebook at DEIB NECSTLab.
During this talk, Andrea Damiani, PhD student in Information Technology at DEIB, Politecnico di Milano, will speak about "Large forests and where to 'Partially' Fit Them".
The Artificial Intelligence of Things (AIoT) calls for on-site Machine Learning inference to overcome the instability in latency and availability of networks. Thus, hardware acceleration is paramount for reaching the Cloud’s modeling performance within an embedded device’s resources. In this talk, we present Entree, the first automatic design flow for deploying the inference of Decision Tree (DT) ensembles over Field-Programmable Gate Arrays (FPGAs) at the network’s edge. It exploits dynamic partial reconfiguration on modern FPGA-enabled Systems-on- a-Chip (SoCs) to accelerate arbitrarily large DT ensembles at a latency a hundred times stabler than software alternatives. Plus, given Entree’s suitability for both hardware designers and non-hardware-savvy developers, we believe it has the potential of helping data scientists to develop a non-Cloud-centric AIoT.
During this talk, Andrea Damiani, PhD student in Information Technology at DEIB, Politecnico di Milano, will speak about "Large forests and where to 'Partially' Fit Them".
The Artificial Intelligence of Things (AIoT) calls for on-site Machine Learning inference to overcome the instability in latency and availability of networks. Thus, hardware acceleration is paramount for reaching the Cloud’s modeling performance within an embedded device’s resources. In this talk, we present Entree, the first automatic design flow for deploying the inference of Decision Tree (DT) ensembles over Field-Programmable Gate Arrays (FPGAs) at the network’s edge. It exploits dynamic partial reconfiguration on modern FPGA-enabled Systems-on- a-Chip (SoCs) to accelerate arbitrarily large DT ensembles at a latency a hundred times stabler than software alternatives. Plus, given Entree’s suitability for both hardware designers and non-hardware-savvy developers, we believe it has the potential of helping data scientists to develop a non-Cloud-centric AIoT.
The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures.
Every week, the “NECSTFridayTalk” invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the “Computing Systems”.
Streaming via Facebook will be available at the following link
