On October 1^st, 2021 at 04:00 pm Francesco Antognazza, DEIB PhD student, will hold a seminar titled "Working with RISC-V: from open ISA to open Architecture to open Hardware", as a part of his Summer School “ACACES 2021”.

In the past few years, the RISC-V instruction set has been of central interest for both academia and industry, being an open standard held by a consortium with an ongoing standardization process and open to contributions and discussions.

Moreover, the definition of multiple instruction set extensions enables the adaptation of RISC-V ISA for a wide range of devices from IoT to HPC, along with the freedom of defining custom instruction set extensions for application-specific designs.

This seminar will present a subset of microcontroller-grade processors developed by the PULP team from ETH Zurich and Università di Bologna, some of which are used in a cluster configuration aiming at extremely energy-efficient computations.

Moreover, the development of a custom instruction set extension will be illustrated, with the final goal of producing a performance boost of AI-based workloads on IoT devices and thus enabling the creation of CPUs tailored for edge-computing scenarios.


Please, note that the event is meant for the internal personnel of the Department.