Cristina Silvano is an Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria. She has recently been named IEEE Fellow (effective from 2017) by the IEEE Boards of Directors “for contributions to energy-efficient computer architectures”. She annually teaches basic and advanced courses on Computer Architectures and Operating Systems. She is currently Project Coordinator of the H2020-FET-HPC Europen Project ANTAREX (2015-2018) on "AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems”. Previously, she was Project Coordinator of two European projects: FP7-2PARMA (2010-2013) and FP7-MULTICUBE (2008-2010). Since 1996, she has started a continuous research collaboration with STMicroelectronics on power-aware embedded architectures. She was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008). She has been nominated Project Manager of the IBM/POLIMI Collaborative Innovation Center on Big Data Analytics (2015-Present).
She is an active contributor to the scientific community and she regularly serves as Member (or Track Chair) of the Program Committee of several top-level conferences such as DAC, ICCAD, DATE, NOCS, HPCA, MICRO, ASAP and FPL. Recently she was Program Chair of FPL 2015, the 25th International Conference on Field Programmable Logic and Applications. Previously, she was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. She was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). From June 2015, she is Associate Editor of ACM Transactions on Architecture and Code optimization (TACO). She has served as Independent Expert Reviewer for the European Commission and for several science foundations such as the Agence National de la Recherche (F), the Swiss National Science Foundation (CH) and the Academy of Finland. She has been invited to give several talks/seminars and moderate panels all over the world.
Her current research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design, design space exploration of embedded architectures, application autotuning for many-core architectures, Network-on-Chip architectures and technology-aware many-core architectures. She is co-author of more than 160 scientific publications on peer-reviewed international journals and conferences (including 17 IEEE/ACM Transactions and collecting one Best Paper Award). She is co-editor of 4 Special Issues and 3 scientific books. She is inventor/co-inventor of 11 international patents (7 out of 11 already granted). Based on Google Scholar (21/11/2016), my h-index is 29, my i10-index is 70 and my total number of citations is 2833.
She started her career as Design Engineer and then become Senior Design Engineer at the R&D Labs of Group Bull in Italy (1987-1996). Since 1992, she was part of the Bull-IBM Research team for the design of the first worldwide multiprocessor system based on PowerPC architecture.
These multiprocessors have been commercialized as Bull Escala UNIX Servers and as IBM RS/6000 Multiprocessor Servers. she also spent several periods abroad as Visiting Engineer at Bull R&D Labs, Billerica (MA - USA), Visiting Engineer at VLSI Technology, in Munich (D) and in S. Jose (CA-USA) and Visiting Engineer at IBM Somerset Design Center, Austin (TX - USA).