On June 26^th, 2023 at 2.00 pm Yuko Hara-Azumi, Professor at Institute of Technology of Tokyo, will give a seminar on "Power Side-channel Countermeasures for High-level Synthesis-designed Cipher Circuits" in DEIB PT1 Room (Building 20).

In the Internet of Things (IoT) era, edge devices have been considerably diversified and are often designed using high-level synthesis (HLS), which translates behavioral descriptions into hardware descriptions, for improved design productivity. However, HLS tools were originally developed in a security-unaware manner, resulting in vulnerabilities to power side-channel attacks (PSCAs), which are a serious threat to IoT systems. Currently, the impact and applicability of existing HLS-based methods to PSCA-resistant designs are limited. In our recent work that was presented at the International Symposium on Field-Programmable Gate Arrays (ISFPGA) 2023, we developed an effective HLS-based design method for PSCA-resistant ciphers implemented in hardware. In particular, we focus on lightweight block ciphers composed of addition/rotation/XOR (ARX)-based permutations to study the effects of the threshold implementation, one of provable countermeasures against PSCAs, to the behavioral descriptions of ciphers along with the changes in HLS scheduling. The results by the security evaluation using an FPGA board demonstrate that our proposed method can successfully improve the resistance against PSCAs for all ARX-based ciphers used as benchmarks.

Yuko Hara-Azumi received her Ph.D. degree in Information Science from Nagoya University, Japan, in 2010. She was a JSPS postdoctoral research fellow at Ritsumeikan University from 2010 to 2012, during which she was also a visiting scholar at University of California, Irvine, USA and Karlsruhe Institute of Technology, Germany. In 2012, she joined Nara Institute of Science and Technology, as an assistant professor. Since 2014, she has been with the Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology, where she is currently an associate professor. Also, she is currently a visiting scholar at Katholieke Universiteit Leuven, Belgium (from April to July, 2023).
Her research interests include system-level design automation, especially on high-level and logic synthesis, microprocessor architecture, and hardware/software co-design for embedded/IoT systems. She has served as an organizing and program committee member of several premier conferences, including DAC, ICCAD, DATE, CASES, ASP-DAC, and FPL.