Searching for common security weaknesses in early stages of RTL implementation
Baleegh Ahmad
PhD Student, New York University
DEIB - 2A Room (Building 20)
April 13th, 2023
2.30 pm
Contacts:
Christian Pilato
Research Line:
System architectures
PhD Student, New York University
DEIB - 2A Room (Building 20)
April 13th, 2023
2.30 pm
Contacts:
Christian Pilato
Research Line:
System architectures
Sommario
On April 13th, 2023 at 2.30 pm Baleegh Ahmad, New York University, will give a seminar on "Searching for common security weaknesses in early stages of RTL implementation" in DEIB 2A Room.
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. In this presentation, we investigate the practical implications and feasibility of producing a set of security-specific scanners that operate on Verilog source files.
The scanners indicate parts of code that might contain one of a set of MITRE’s common weakness enumerations (CWEs). We prototype scanners and evaluate them on 11 open source designs and explore the nature of identified weaknesses. We will also discuss the use of Large Language models to repair some of these weaknesses.
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. In this presentation, we investigate the practical implications and feasibility of producing a set of security-specific scanners that operate on Verilog source files.
The scanners indicate parts of code that might contain one of a set of MITRE’s common weakness enumerations (CWEs). We prototype scanners and evaluate them on 11 open source designs and explore the nature of identified weaknesses. We will also discuss the use of Large Language models to repair some of these weaknesses.
Biografia
Baleegh is an Electrical Engineering PhD Student at NYU Tandon. His research interests include detection and repair of bugs at Register Transfer Level (RTL) and using LLMs to write Hardware Design Language code. Before joining NYU Tandon, Baleegh did his undergraduate studies at NYU Abu Dhabi.
