Over the past decade, deep learning techniques have benefited a large number of Artificial Intelligence applications, like computer vision and speech recognition. Among others, Convolutional Neural Networks (CNNs) have become the state-of-the-art class of algorithms for image recognition and classification, and represent one of the hottest topics of research for both academia and industry. The even larger amount of processing required by these networks, however, is making general purpose CPU processors unsuitable to efficiently handle the wide range of real-life applications, which spread from embedded systems to cloud computing, leaving thus large rooms for heterogeneous architectures to tackle the CNN's computational intensity. Specifically, Field Programmable Gate Arrays (FPGAs) are becoming an attractive solution to accelerate CNNs, thanks to both their reconfigurability and energy efficiency properties. The presented work shows an IP cores library for CNNs' acceleration targeting FPGA devices. This library implements the most used networks' computational patterns, i.e. convolution, sub-sampling and fully-connected kernels. These kernels can be widely parametrized to guarantee a full coverage of the network's structure, as well as to easily apply hardware-related optimizations and to automatically achieve several kinds of parallelisms. Each kernel relies on dedicated design techniques -- such as optimal on-chip memory buffering and time-sharing -- aimed to improve performances while guaranteeing modularity, allowing thus to leverage the same IPs to efficiently design CNNs targeting different FPGA families. To balance both resources utilizations and latency of each network's stage, an analytical resource and performance models of each component have been developed, and their accuracy has been tested on two real use cases targeting embedded and high-end FPGAs.

The NECSTLab is a DEIB laboratory, with different research lines on advanced topics in computing systems: from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures. Every week, the “NECST Friday Talk” invites researchers, professionals or entrepreneurs to share their work experiences and projects they are implementing in the “Computing Systems”.