Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If an attacker gets hold of an unprotected IC, he can reverse engineer the IC and pirate the IP.  Similarly, if an attacker gets hold of a design, she can insert malicious circuits and backdoors into the design.
In this talk I will outline design-for-trust techniques that we developed to prevent these and similar attacks: IC camouflaging, logic encryption, and split manufacturing. IC camouflaging modifies the layout of various gates in the IC to deceive attackers into obtaining an incorrect netlist, preventing reverse engineering. Split manufacturing divides the layout and manufactures them at two separate foundries to stop reverse engineering and piracy by a malicious foundry. Logic encryption implements a built-in locking mechanism in ICs to prevent reverse engineering and IP piracy by a malicious foundry and user.
I will wrap up the presentation by pointing out why hardware security is an essential objective from economics, security, and safety aspects and offer my vision of the developing field of hardware cybersecurity.

Ramesh Karri is a Professor of Electrical and Computer Engineering at New York University. He co-directs the NYU Center for Cyber Security. He is also leads the Cyber Security thrust of the NY State Center for Advanced Telecommunications Technologies at NYU. He co-founded the Trust-Hub and organizes the Embedded Systems Challenge, the annual red team blue team event.
Ramesh Karri has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego and a B.E in ECE from Andhra University. His research and education activities in hardware cybersecurity include trustworthy ICs; processors and cyber-physical systems; security-aware computer-aided design, test, verification, validation, and reliability; nano meets security; hardware security competitions, benchmarks and metrics; biochip security; additive manufacturing security.  He has published over 200 articles in leading journals and conference proceedings.