Semiconductor companies like STMicroelectronics utilize specialized roles dedicated to the verification of the functional correctness of a chip. The purpose is to eliminate nearly all the functional defects (bugs) of a device before manufacturing it in order to avoid costly re-spins. In an Integrated Circuit market, where the cost to design and manufacture a chip is growing exponentially, the role of the Verification Engineer is becoming more and more important.
During the talk, STMicroelectronics verification experts will explain what is the verification, which are the most used methodologies in the field and will introduce some verification techniques applied in the context of the networking IP.

Alberto Allara is currently a Functional Verification Manager in the DMA Group at STMicroelectronics (Italy) where he leads a Verification team. He received a Master Degree in Electronic Engineering in 1994 from Politecnico di Milano (Italy) and a post-degree Master in Information Technology from Cefriel-Politecnico di Milano in 1996. He started his career in 1996 as a Digital Designer working also on research projects funded by the European Community and dealing with formal verification and high-level synthesis. Since 2002 he has been working as Verification Engineer. He has experience on verification of complex data-intensive mixed-signal IPs as well as on the verification of complex multi-core Systems-on-chips both in Simulation and Co-emulation.

Matteo Barbati received his Master Degree in Computer Science at “Politecnico di Milano” in 2005. After a brief experience as Researcher at Politecnico di Milano, from 2006 to 2011 he worked in STMicroelectronics as IP Verification engineer. From 2011 to 2015 he worked as Digital Designer in Yogitech. Since 2015 he is working in STMicroelectronics as Verification Engineer, focusing on SerDes verification and on High-Speed IP Verification. He co-authored 4 papers in international conferences specialized in Verification.