From custom hardware to SHAD: High Performance Analytics in the era of Big Data
Vito Giovanni Castellana
Pacific Northwest National Laboratory (PNNL)
DEIB - PT1 Room (building 20, ground floor)
December 17th, 2018
10.30 am
Contacts:
Fabrizio Ferrandi
Research Line:
System architectures
Pacific Northwest National Laboratory (PNNL)
DEIB - PT1 Room (building 20, ground floor)
December 17th, 2018
10.30 am
Contacts:
Fabrizio Ferrandi
Research Line:
System architectures
Abstract
Emerging applications in different domains, ranging from scientific simulations to machine learning and data analytics, are increasingly affected by issues known as the 5 “V”s of Big Data: Volume, Velocity, Variety, Variability and Value. Processing an unprecedented volume of heterogeneous data that is rapidly changing poses novel challenges to industry and the research community: under these working conditions, providing High-Performance, scalable, and versatile solutions becomes a fundamental requirement.
In this talk, Dr. Castellana will overview recent, ongoing, and, upcoming research efforts at Pacific Northwest National Laboratory, with particular focus on graph and big data analytics workloads.
He will discuss different apporaches to tackle the Big Data challenges, including hardware specialization via custom accelerators, HW/SW co-designed systems, software stacks for commodity hardware, and, software libraries.
He will finally introduce SHAD, the Scalable High-performance Algorithms and Data-structures library, which aims at addressing scalability and performance issues typical of data analytics applications, while providing flexibility and high productivity.
SHAD’s core is built on an Abstract Runtime Interface which enhances portability across multiple platforms. The core library includes general purpose algorithms and data-structures, designed to accommodate and process, in massively parallel envorinments, significant amounts of data.
SHAD containers are also used as building blocks for SHAD extensions, i.e. higher level software libraries. Among these, SHAD currently offers a Graph Library extension.
SHAD is currently available at github.com/pnnl/SHAD, under Apache license.
In this talk, Dr. Castellana will overview recent, ongoing, and, upcoming research efforts at Pacific Northwest National Laboratory, with particular focus on graph and big data analytics workloads.
He will discuss different apporaches to tackle the Big Data challenges, including hardware specialization via custom accelerators, HW/SW co-designed systems, software stacks for commodity hardware, and, software libraries.
He will finally introduce SHAD, the Scalable High-performance Algorithms and Data-structures library, which aims at addressing scalability and performance issues typical of data analytics applications, while providing flexibility and high productivity.
SHAD’s core is built on an Abstract Runtime Interface which enhances portability across multiple platforms. The core library includes general purpose algorithms and data-structures, designed to accommodate and process, in massively parallel envorinments, significant amounts of data.
SHAD containers are also used as building blocks for SHAD extensions, i.e. higher level software libraries. Among these, SHAD currently offers a Graph Library extension.
SHAD is currently available at github.com/pnnl/SHAD, under Apache license.
Short Bio
Vito Giovanni Castellana is a research scientist in the High Performance Computing Group at Pacific Northwest National Laboratory (PNNL). His research interests include embedded system design and electronic design automation, code transformation, compilation, and optimization, in particular in the domain of data analytics and irregular applications.
In addition to the SHAD library, he has been one of the main designers and developers of GEMS, Graph Engine for Multithreaded Systems, and the GraQL query language. He has also contributed to several open source projects, such as the Global Memory and Threading (GMT) runtime library, and Politecnico's Bambu High Level Synthesis tool, investigating new hardware solutions and methodologies for the synthesis of custom hardware accelerators.
Castellana received a PhD in computer science and engineering from Politecnico di Milano, Italy.
In addition to the SHAD library, he has been one of the main designers and developers of GEMS, Graph Engine for Multithreaded Systems, and the GraQL query language. He has also contributed to several open source projects, such as the Global Memory and Threading (GMT) runtime library, and Politecnico's Bambu High Level Synthesis tool, investigating new hardware solutions and methodologies for the synthesis of custom hardware accelerators.
Castellana received a PhD in computer science and engineering from Politecnico di Milano, Italy.