Electronics > High-Performance Frequency Synthesizer for Wireless Systems (HPFS)

Project abstract

The implementation of radios in low-cost CMOS processes for cellular (GSM/EDGE) and WiFi (802.11) standards is today possible. However, the evolution of communication standards towards higher bit rates (WCDMA and WiMax 802.16e) requires new improvements in terms of circuit noise and bandwidth. In particular, the frequency synthesizer, employed in the radio as local oscillator, needs to scale jitter down to hundreds of femtoseconds, while maintaining very high frequency resolution. Thanks to the aggressive scaling of CMOS processes, performance can be improved by employing more and more advanced background calibrations of analog circuits at low additional cost. A fully-integrated 3.0-to-3.6GHz frequency synthesizer with 3MHz bandwidth, rms jitter lower than 800fs and spurs lower than 57dBc has been successfully demonstrated in 65-nm CMOS. This synthesizer employs a digital programmable filter, two new background algorithms for spur cancellation and an innovative technique for the suppression of flicker noise in voltage-controlled oscillators. HPFS is a research project supported by public bodies (EU and MIUR) and by semiconductor companies (Intel, USA).

3.0-to-3.6GHz All-Digital PLL in 65nm CMOS

Project results

Three patents have been so far filed.