Computer Science and Engineering > Synaptic

Project abstract

The project targets several different abstraction levels seen through a design flow targeting regular approaches for the fabrication of digital devices. The project intends to verify the role of applying regularity at different levels compared to a golden design flow used as reference.
The Synaptic project addresses the Program call by developing “methods and tools to cope with the design challenges in the next generations of technologies” and focuses on the objective “design for manufacturability taking into account increased variability of new processes”. In particular, the project targets the optimization of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels.
We propose the creation of a methodology and associated suite of design tools which extract regularity at the architectural and structural level and automate the creation of regular compound cells which implement the functionality of the extracted templates.
The project develops a new design methodology in which the concept of regularity is propagated through all abstraction levels:

  • Architectural - the advantages of the proposed methodology include the ability to exploit complex logic cells and building blocks, thus providing greater predictability of design performance and enabling comprehensive early architecture exploration.
  • Logic - the advantages include the creation of logic cell libraries targeted to design requirements, thus improving performance and performance predictability.
  • Physical - this approach will enable the use of lower-cost lithography techniques as compared to existing approaches. This makes it cost-effective to use more advanced lithography techniques, thus enabling the use of more advanced semiconductor technologies.
Through use of a more restrictive set of layout patterns with predictable layout neighborhood, variability caused by the physical limitations of current industrial lithography techniques can be reduced and manufacturing yield can be improved. In particular, for implementation of random logic, the layout restrictions lead to loss of density of the logic cell libraries when compared with traditional methodology.
To enable technology scaling to remain attractive, it is necessary to counter the negative effects of regularity restrictions on logic density. It is therefore critically important to focus research efforts on developing innovative design methodologies, which remove these limitations.

Project results

Publications:

C. Pilato, F. Ferrandi and D. Pandini, "A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells," in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), pp. 23-28, 2010.