Present position: Assistant Professor
|Thesis title:||Dynamic Compilation for Architectures with Instruction-Level Parallelism|
|Advisor:||Stefano Crespi Reghizzi|
|Research area:||Systems Architectures|
The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, and these two technologies offer different benefits, namely high code portability and low power consumption and hardware costs. The adoption of dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to the need for software instruction scheduling that characterizes the VLIW architectures.
The project described in this dissertation aims at exploring the possibilities of applying JIT translation of Jabva Bytecode on systems based on VLIW processors, exploiting the instruction-level parallelism as much as possible. In particular, we describe the architecture and optimization passes of JIST, a scheduling JIT compiler, based on the open source Java Virtual Machine implementation Kaffe, and targeted to the Lx platform, a family of Very Long Instruction Word processors jointly developed by Hewlett Packard and STMicroelectronics. Within this framework, three main issues require consideration: register allocation, instruction scheduling, and memory disambiguation.
We show the impact of these optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmarks programs. We report speedups ranging from 20% to 46% and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JIT compiler.