|Thesis title:||Reliability Issues in Ultra-Scaled Flash Memories|
|Advisor:||Andrea L. Lacaita|
|Research area:||Microelectronics and Emerging Technologies|
The constant improvements in the silicon technology exhibited over the years by the semiconductor industries have resulted in a continuous reduction of the electron devices feature size. These technological developments strongly impact in device performance and production costs.
One of the most important reliability issues in the last technological nodes is the Random Telegraph Noise (RTN). This is phenomenon affects the threshold voltage VT of the memory cell.
The correct VT reading is required to read correctly the information stored in the device.
Beyond the 60 nm technology node, the granularity of the charge stored in the device is not more negligible and this fact influences the accuracy to perform the program operation. This means that the statistical nature of the electrons injection into the floating gate spreads the VT distribution of the array cells. The feature size reduction affects negatively the distribution because spread becomes wider (less electrons are necessary to program the cell, roughly few hundreds) and it becomes more and more difficult to control the cell VT by the program algorithm.
Another issue began to show its effects in sub-100 nm technologies concerns the cells interference. The cells floating gates are so close each other that a cross-talk is established by the field oxide among the gate stacks. A VT change is observed during the reading operation and, especially, in the retention phase. The VT loss displays a dependence on the program pattern of the adjacent cells, thus modeling and characterization of both program and erase transients have been performed to understand the nature of this aspect.
These phenomena contribute all together to corrupt the data stored, causing the memory failure and thus the worn-out.