Present position: Microelectronic Engineer at the European Space Agency Research and Technology Center (ESTEC)
|Thesis title:||MPSoCs: Methods and Techniques to Tackle Design Complexity|
|Research area:||Systems architectures|
This thesis presents ReSP (Reflective Simulation Platform), a Transaction
Level multi-processor simulation platform based on the integration of SystemC and Python.
ReSP exploits the concept of reflection enabling the integration
of SystemC components without source code modifications,
and providing full observability of their internal state.
ReSP offers fine-grained simulation control and supports the evaluation of different hardware/software
configurations of a given application,
enabling complete design space exploration.
ReSP allows the evaluation of real-time applications on high-level hardware models since it provides the
transparent emulation of POSIX-compliant Real Time Operating Systems (RTOS) primitives.
A number of experiments has been performed to validate ReSP
and its capabilities, using a set of single- and multi-threaded benchmarks, with
both POSIX Threads and OpenMP programming styles.
These experiments confirm that reflection introduces negligible (<1%) overhead when
comparing ReSP to plain SystemC simulation.
Results also show that ReSP can be successfully used to analyze and explore
concurrent and reconfigurable applications even at very early development stages.
In fact, the average error introduced by ReSP's RTOS emulation is below $6.6pm5%$ w.r.t. the same RTOS running
on an ISS while simulation speed increases of a factor $10$.
Thanks to the integration with a scripted language, simulation management is
simplified and experiments set-up effort is considerably reduced.