Computing with FPGA-based accelerators (from HiPEAC ACACES 2015 summer school)
Pietro Fezzardi
DEIB PhD Student
DEIB - 2A Room
October 9th, 2015
3.30 pm
Research Line:
System Architectures
Sommario
The seminar is based on the course attended at the HiPEAC ACACES 2015 summer school. The presentation will provide an introduction to Field Programmable Gate Arrays, at functional and architectural level. The typical design flow for FPGAs will be described, with an overview of the steps involved in HW synthesis and the algorithms used in the process. Finally, the talk will focus on High-Level Synthesis for FPGAs, the advantages it can bring to traditional HW synthesis and some of its challenges.