Processors are experiencing increasing soft error rates as the feature size of CMOS process technology shrinks. While the SRAM structures on chip have been protected via ECC, the execution units remain vulnerable. Many solutions, both hardware and software, have been proposed to deal with this problem, such as hardware or software duplication or triplication, parity, or residue codes. They all have high performance and/or power overheads that are typically not acceptable. Many of the techniques can detect faults but are not able to correct them.

This work proposes to use vector instructions available in all major processors to replace instruction duplication with operation duplication and checking. This has a much lower overhead and is applicable to all ALU instructions. The cost of this redundant execution is significantly lower and, if correction is required, it can be easily added. We prototyped the system using Intel vector intrinsics for SSE and AVX f.p. instructions. The results show that, compared to error detection through scalar instruction duplication, the proposed vector mode redundant execution is 1.78x and 2.73x faster, on average, for SSE and AVX f.p. instructions, respectively.
It also reduces the energy consumption by an average of 40% and 53%, respectively, for the corresponding cases. The proposed technique thus enables error detection with no additional hardware cost and reduced time and energy overhead compared to scalar instruction duplication.

Alexander V. Veidenbaum holds a PhD degree in Computer Science from the University of Illinois at Urbana-Champaign. He is Professor of Computer Science at the University of California, Irvine. His research interests are computer architecture and compiler optimization for parallel, high-performance, embedded and low-power systems. He is a member of the ACM, the IEEE and the IEEE Computer Society.