The Internet of Things (IoT) has now become a main driver in research and next-generation technology development, and is expected to foster the growth of the semiconductor industry in the next decade or more, as the wave of mobile platforms is reaching its saturation.
In spite of daily announcements of new industrial projects in the IoT domain, the physical nodes that gather sensed data (the “things”) are still technologically immature, and well behind the rest of the IoT infrastructure. This lag has been determined by several daunting challenges in terms of energy efficiency and security under tight cost constraints, as well as a rigid view on the quality of service provided by IoT nodes. Energy efficiency is indeed synonym for node availability and size, whereas cheap chip-level security is a necessary premise to build adequate trust in the minds of potential adopters.
This talk addresses these fundamental issues and sketches a map to move towards the true realization of the physical layer of IoT, and ultimately enable IoT nodes with extreme energy efficiency and unceasing security, in both space (across nodes) and time (in each node). The scalable quality of service in IoT nodes is shown to be a key ingredient to relax the critical design tradeoffs, and generalize the well-known concept of “QoS” that is ubiquitously applied in the Internet of today. A perspective is finally given on the future role of technology and EDA industry in the IoT arena, based on the natural bottom-up (business) pressure that has made the Internet possible in the past. And will make the Internet of Things real in the future, well beyond the current wave of simple smartwatches.

Massimo Alioto is Associate Professor at the ECE Department of the National University of Singapore, where he leads the Integrated Circuits and Embedded Systems area (80+ people) and the Green IC group. Previously, he was Visiting Scientist at Intel Labs – CRL (2013), Visiting Professor at the University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL – Lausanne (2007), and Associate Professor at the University of Siena.
He is (co)author of 220 publications on journals (80, mostly IEEE Transactions) and conference proceedings, and two books with Springer. His primary research interests include ultra-low power VLSI circuits, self-powered/wireless nodes, near-threshold circuits for green computing, energy-quality scalable VLSI circuits, circuits for HW-level security and on-chip learning.
He is currently Associate Editor in Chief of the IEEE Transactions on VLSI Systems. He also serves or has served as Associate Editor of several IEEE and ACM journals. He served as Guest Editor of various journal special issues (e.g., “Ultra-Low Voltage Circuits and Systems for Green Computing” on IEEE TCAS-II). He is/was Technical Program Chair of several IEEE conferences (e.g., SOCC, ICECS, VARI, NEWCAS, PRIME, ICM), and Track Chair in several others (e.g., ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). In the last five years, he has given 50+ invited talks in top universities and leading semiconductor companies. He is/was Distinguished Lecturer (2009-2010) and member of the Board of Governors of the IEEE Circuits and Systems Society (2015-2016). He is an IEEE Fellow.