Field Programmable Gate Arrays (FPGAs) are reconfigurable hardware devices that allow the developer to create circuits with specific and dedicated functions. One of the main trends on FPGA usage is hardware acceleration. In this scenario, the developer designs an ad-hoc circuit in order to hardware accelerate certain parts of an algorithm, usually the computational kernel. As result, for specific computational patters, FPGAs are able to outperform CPUs and GPUs thanks to a better performance per watt ratio.
One of the main difficulties in approaching FPGAs is its steep learning curve. In fact, FPGAs are usually programmed by means of Hardware Description Languages (HDLs), like VHDL or Verilog, therefore it is complex and time-consuming design the complete circuit. To (partially) solve this issue, different companies have developed tools for High Level Synthesis (HLS), in order to allow developers to program FPGAs with high level languagues. One of these tools is MaxCompiler, developed by Maxeler Technologies, which permits to used MaxJ, a set of libraries for Java, in order to accelerate the computational kernel of applications. Nonetheless, such kernels have to be designed in a dataflow fashion way, hence it takes time to understand how to properly and efficiently develop code for Maxeler FPGAs, also called Dataflow Engines (DFEs). This talk presents C2MAXJ, a tool able to generate synthesizable and optimized code for Maxeler DFEs starting from C/C++ code. Such a tool relies on LLVM Compiler Infrastructure and targets the Intermediate Representation (IR) of LLVM, where most of the architecture independent optimizations are applied. The tool manipulates the IR in order to generate a dataflow graph of the computational kernel of the application and, finally, translates it into MaxJ.