Emerging Big Data applications require a significant amount of server computational power. Big data analytics applications rely heavily on specific deep machine learning and data mining algorithms, and exhibit high computational intensity, memory intensity, I/O intensity and control intensity. Big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However, the rapid growth in the data yields challenges to process them efficiently using current server architectures such as big Xeon cores. Furthermore, physical design constraints, such as power and density, have become the dominant limiting factor for scaling out servers. To respond to this power challenge, which sometimes referred as Dark Silicon, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk, through methodical investigation of power and performance measurements, and comprehensive system level and micro-architectural analysis, I first show the characterization results of emerging big data applications on big Xeon and little Atom-based server architecture. The characterization results across a wide range of real-world big data applications and various software stacks demonstrate how the choice of big vs little core-based server for energy-efficiency is significantly influenced by the size of data, performance constraints, and presence of accelerator. Furthermore, the microarchitecture-level analysis highlights where improvement is needed in big and little cores microarchitecture. Second, I will show how in a heterogeneous architecture effective mapping of Hadoop MapReduce based big data applications to FPGA accelerator can significantly increase the energy-efficiency and performance. The results show promising kernel speedup of more than 100X and significant energy-efficiency gains that can be achieved with FPGA acceleration.

Houman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science. He is the director of GMU’s Green Computing and Heterogeneous Architectures (GOAL) Laboratory. Prior to joining George Mason University, Houman spent two years at the University of California, San Diego, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC).
Houman’s research is in big data computing, heterogeneous computing, computer architecture, embedded system design, memory design, DRAM Design, green and low power computing, and spans the areas of computer design and embedded systems, where he has published more than 70 technical papers in the most prestigious conferences and journals on the subject. He is currently leading a number of research projects, including the design of next generation heterogeneous architecture for big data processing, non- volatile STT logic to prevent design reverse engineering, heterogeneous accelerator platforms for wearable biomedical computing, and logical vanishable design to enhance hardware security which are all funded by National Science Foundation (NSF), General Motors Company (GM), National Institute of Standards and Technology (NIST) and Defense Advanced Research Projects Agency (DARPA). Houman was a recipient of the four-year University of California, Irvine Computer Science Department chair fellowship. He received his PhD degree from the Department of Computer Science at the University of California, Irvine in 2010, an MS degree in computer engineering in 2005 from University of Victoria, Canada and his BS degree in electrical engineering in 2003 from Sharif University of technology.