Improving performance per Watt of Multicores

Improving the Performance per Watt of Asymmetric Multicores via Online Phase Classification, Adaptive Core Morphing and Dynamic Thread Scheduling

Israel Koren
Professor of Electrical and Computer Engineering
University of Massachusetts (UMass)

DEI - Sala Seminari
6 luglio 2012
Ore 11.15

Abstract:

Asymmetric multicores (AMPs) have been shown to outperform symmetric ones in terms of performance and performance/watt. The improved performance and power efficiency are achieved when the program threads are matched to their most suitable cores. Since programs change their computational needs during their execution, the best thread to core assignment will likely change with time. We have therefore, developed an online program phase classification scheme that allows swapping of threads when the current needs of the threads justify a change in the assignment. The architectural differences among the cores in an AMP can never match the diversity that exists among different programs and even between different phases of the same program. Thus, we must expect to see program phases where the designed cores will be unable to support the ILP that the program can exhibit. We therefore, propose in this talk a dynamic morphing scheme. This scheme will allow a core to gain control of a functional unit that is ordinarily under control of a neighboring core, during periods of dense computation with high ILP. This way, we dynamically adjust the hardware resources to the current needs of the application. Our results show that combining online phase classification and dynamic core morphing can significantly improve the performance/watt of most multi-threaded workloads.

Short Bio:

Affiliation and memberships

  • professor of Electrical and Computer Engineering at the University of Massachusetts at Amherst
  • fellow of the IEEE
Consulting activity
  • IBM, Analog Devices, Intel, AMD and National Semiconductor
Research interests (include)
  • fault-tolerant systems
  • secure cryptographic devices
  • VLSI yield and reliability
  • computer architecture
  • computer arithmetic
  • publications
    • over 250 in refereed journals and conferences
    Books
    • “Computer Arithmetic Algorithms”, 2nd Edition, A. K. Peters, Ltd., 2002
    • “Fault-Tolerant Systems”, Morgan-Kaufman, 2007 (as co-author)


    Contatti:
    Luca Breveglieri

    Area di ricerca:
    Architetture