Methods and tools to cope with the design challenges ...

Methods and tools to cope with the design challenges in the next generations of technologies

May 16th, 2012
9.00 am - 4.00 pm
Politecnico di Milano
Dipartimento di Elettronica e Informazione
Seminar Room


Abstract:
It is widely accepted that one of the major challenges in electronic design automation (EDA) is design for manufacturing (DFM). In general terms DFM is defined as a set of techniques adopted to estimate, control, and improve the yield and robustness of a circuit before fabrication.
Yield loss in Integrated Circuits (ICs) can be decomposed into three factors: Defect density, Lithography-based, and Parametric-based. Defect density related yield loss is relatively controlled, but the other two components are increasingly important in nanoscale integrated circuits. Lithography-based yield loss is related to sub-wavelength lithography failures, causing either shorts or opens in the different layers. Parametric-based yield loss occurs because the manufactured chip does not meet a design parameter, like frequency or power dissipation. This last component of yield loss occurs because there is a large dispersion in circuit parameters due to process variations. It is important to note that a large part of process variations are also due to imperfections in lithography, and therefore, lithography-based problems impact both parametric yield loss and catastrophic lithography yield loss.
Optical lithography is the main process used in the Integrated Circuit (IC) industry to manufacture products. Unfortunately, optical lithography encounters serious limitations as we enter the Deep Sub-Micron era (DSM) which cause a serious decrease in yield and therefore jeopardises the advantages provided by technology scaling. As we enter the Deep Sub-Micron era, optical lithography IC manufacturing processes need new solutions to manufacture products at low cost. Process variations pose many challenges for circuit design due to their effects on performance, power and yield. First, process variations decrease the predictability of circuit delay and power dissipation thus increasing the design time because of the difficulty of verifying and testing the resulting circuits. This circuit unpredictability has led to the concept of frequency binning, which is very costly in terms of performance (and hence, revenue) because many units perform worse than desired due to process variations. Process variations also reduce yield. This results in more time and investment required to increase yield to acceptable mass scale production levels, and therefore, in an increase of the time-to-market.

A preliminary program can be found at https://web50.dmz.polimi.it/. The seminar is free and all are welcome to attend any and all sessions that are of interest.
To register to the event, please fill in the online registration form or send an email to ferrandi@elet.polimi.it.

Contacts:
Fabrizio Ferrandi

Research area:
Systems architectures