An Efficient Pile-Up Rejector for the Readout ASIC of the HTRS Instrument

An Efficient Pile-Up Rejector for the Readout ASIC of the HTRS Instrument
Alessandro Tocchio
PhD Student

DEI Building 24 - Beta Room
November 22nd, 2010


The combination of very high counting rates and the excellent energy resolution required by the HTRS project presents some important design issues for the realization of a suitable readout ASIC.
All modern spectrometer pulse processors adopt a method for preventing the analysis of pulses whose amplitude is subject to interference of other signals in close time proximity. This function is known in the literature as pile-up rejector.
In general, the pile-up rejector is constituted by two main elements: a parallel fast channel, characterized by a narrow shaping amplifier which allows to discriminate very near events and a pile-up rejection logic. The fast discriminator channel produces logic signals when a pile-up event is detected, while the pile-up rejection logic is usually adopted to analyze those signals and to disable the output of the slow channel by for instance grounding the peak stretcher output. In the present work, a detailed examination of the pile-up rejection process is presented, and it is shown that relevant improvements can be done with respect to previous adopted methods. Finally, the architecture of the pile-up rejector proposed for the HTRS instrument, which enable to analyze incident radiation in the range of energy 0.3 keV to 20 keV at the input rate of 105 cps with ~ 10 % of lost events, is presented.

Alessandro Tocchio

Research Area:
Sensors and instrumentation