DEI - Seminar room
June 24th, 2010
When developing heterogeneous embedded systems, custom hardware accelerators are known to outperform the corresponding software solutions by different orders of magnitude, but the resources for their implementation are usually limited in the final architecture.
Unfortunately, even if the synthesis of behavioral specifications has been a hot topic for research for the last two decades and significant achievements have been obtained, existing methodologies are usually able to generate only one-shot high-quality solution and design space exploration has usually to be manually performed, for example, by constraining the resources.
In fact, when implementing a single task, the designer cannot know in advance which is the best hardware solution, but he/she should be able to explore them at different level of abstractions: the proper RTL architectures have to be identified and optimized at logical level and, then, the different high-quality Pareto-optimal solutions should be properly selected and combined at system-level, based on the requirements of the application and the constraints of the target architecture.
In this talk, I will present the design exploration framework that we are currently developing at Politecnico di Milano. In particular, we will present how to generate multiple implementations both for FPGAs and ASICs directly from a C specification and, then, how to optimize them at logical level, also exploiting tools for cell library generation. We will also present and discuss the preliminary results that we achieved in the FP7 Synaptic project and the collaboration with Nangate A/S (Copenhangen, Denmark).