DEI - Seminar Room
June 21st, 2010
Heterogeneous multiprocessor architectures are the de-facto standard for embedded system design. Today, to accelerate the different parts of the applications, they are usually composed of several general purpose, digital signal and hardware accelerators (e.g., Field Programmable Gate Arrays - FPGAs or Application Specific Integrated Circuits), interconnected through various communication mechanisms.
When developing an application on such embedded systems, the designer has to determine when (scheduling) and where (mapping) the groups of operations (i.e., the tasks) and the data transfers (i.e., the communications) should be executed, depending on a set of constraints and dependences, in order to optimize some design metrics, e.g., the program execution time. Moreover, differenty implementations are usually available for each task also on the same component and additional constraints are usually imposed on the mapping.
In this talk, we will present our methodology for mapping and scheduling acyclic applications based on Ant Colony Optimization and its extension to approach cyclic applications. We will also discuss the corresponding results that we obtained in the FP6 hArtes project.