Seminario: "A Novel Modular Approach to C-to-HDL Compilation for FPGA Accelerators"
Prof. Walid A. Najjar
University of California Riverside

DEI - Sala Conferenze
Ore 15.15


While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option for faster computing with very large speed-ups, their programmability remains a major barrier to their wider acceptance by application code developers. These platforms are typically programmed in a low level hardware description language, a skill not common among application developers and a process that is often tedious and error-prone. Programming FPGAs from high-level languages would provide easier integration with software systems as well as open up hardware accelerators to a wider spectrum of application developers.
This talk describes ROCCC 2.0, a C-to-HDL compiler toolset, that takes an innovative approach to the generation of FPGA-based hardware accelerators. It relies on a modular, bottom-up, design that allows the programmer a finer control over the resulting circuit on the FPGA. A module, in ROCCC 2.0, is a fully functional C entity that is compiled to a standalone circuit. Other modules can be imported in the design of a module. A module can exist as C code, VHDL code, or a netlist. Existing modules are stored in an integrated database that also records their characteristics such as area (for a specific device family), operating frequency, and pipeline stages. Existing IP cores can be imported as pre-existing modules. The modular C code functions identically as software or hardware. The ROCCC 2.0 code generation relies on abstractions of memory and stream interfaces, it separates the generation of the HDL code from the specifics of a particular platform thereby providing code reuse and fast platform re-targeting. The ROCCC toolset supports an extensive set of compiler transformations aimed at increasing parallelism, throughput and clock frequency while reducing FPGA area and off-chip memory accesses.

Short bio:
Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His research interests are in the fields of computer architecture and compiler optimizations, embedded systems and sensor networks. Lately, he has been very active in the area of compilation for FPGA-based code acceleration and reconfigurable computing. NSF, DARPA and various industry sponsors have supported his research. He received a B.E. in Electrical Engineering from the American University of Beirut in 1979 and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. He was on the faculty of the Department of Computer Science at Colorado State University (from 1989 to 2000), before that he was with the USC-Information Sciences Institute. He currently serves as Associate Editor for IEEE Transactions on Computers and IEEE Computer Architecture Letters. He has served on the program committees for a number of leading conferences including FPL, FPT, CASES, ISSS-CODES, DATE, Computing Frontiers, ICCD, HPCA, and MICRO. He is a Fellow of the IEEE and the AAAS.

Cristina Silvano

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