Graph databases often employ pointer or linked list-based data structures. Although they are convenient to represents dynamically changing relationships among the data elements, they induce an irregular behavior with many unpredictable fine-grained data accesses and they require many synchronization operations. Conventional general-purpose architectures are optimized for locality and reduced access latency, and do not cope well with these workloads, making application-specific accelerators (implemented, for example, on Field Programmable Gate Arrays) an appealing solution. We have developed a set of novel architectural templates and HLS methodologies to automatically generate efficient accelerators from GEMS (Graph Engine for Multithreaded Systems), our graph database for commodity homogeneous clusters based on the Resource Description Framework (RDF) and the SPARQL query language.
In this research study the Intel HARP platform will be exploited to extend our studies and to implement a fully working prototype of our approach on a heterogeneous platform. The study will focus on analysing the close coupling of accelerators with general purpose processors and the impact on caching, coherency, and data transport. Moreover, scalability studies will be performed to identify bottlenecks, and devise news solutions to enhance scalability of the approaches on multinode systems. This research will be jointly developed by Politecnico di Milano and Pacific Northwest National Laboratory.