FASTER, a 36 months project started on September 1st 2011, will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. The project will provide tools that allow to include dynamically reconfigurable hardware accelerators into embedded systems that will allow reaching this goal.
FASTER will develop novel techniques for optimizing and verifying static and dynamic aspects of a reconfigurable design, while minimizing run-time overheads on speed, area and power consumption. FASTER will also provide a powerful run-time system that will be able to run on multiple reconfigurable platforms and manage the various aspects of parallelism and adaptivity with reduced overhead.
To demonstrate the effectiveness of the FASTER tool-chain, we will use three complex applications from different application domains:

1. Reverse Time Migration (RTM), a computational seismography algorithm,
2. Global Illumination and Image Analysis,
3. a Network Intrusion Detection System (NIDS).

Project performance targets:

• 20% productivity improvement due to seamless implementation and verification of dynamically changing systems
• 50% total ownership cost reduction for NIDS and RTM systems
• 2x performance improvement under power constraints for Global Illumination and Image Analysis