HEAP Lab Talk
Mobile Main Memories: System and Technology
Paolo Amato
Emanuele Confalonieri
Marco Sforzin
Politecnico di Milano - D11 Room (Building 25, ground floor - Via Golgi n. 40, Milano)
December 13th, 2017
1.15 pm - 3.15 pm
Contact:
Francesca Micol Rossi
Research Line:
System architectures
Paolo Amato
Emanuele Confalonieri
Marco Sforzin
Politecnico di Milano - D11 Room (Building 25, ground floor - Via Golgi n. 40, Milano)
December 13th, 2017
1.15 pm - 3.15 pm
Contact:
Francesca Micol Rossi
Research Line:
System architectures
Abstract
On December 13th, 2017 at 1.30 pm, “Mobile Main Memories: System and Technology” seminar will be held in D11 Room, as new appointment of HEAP Lab Talks.
Memories are a key component of all computing systems. Just think that last year DRAM market has reached the value of 69B$, out of 400B$ of the whole semiconductor market. Moreover, the market feels a further boost to growth: users are eager of devices with always increasing performance which includes speed, power and capacity.
In order to meet the expected performance growth and to follow the evolving market requirements, main memory system must improve in size, technology, efficiency, cost, and management algorithms.
But mainstream memory technologies are reaching their scaling limits. Thus it’s paramount to work on different approaches: modify how the system uses main memory, change the architecture of memory devices, enable alternative technologies (emerging memories like 3D XPoint), and add functionalities to the memory systems (like error correcting codes and security primitives).
In this talk we’ll focus on mobile memories, which account for almost 50% of DRAM bits.
In particular we’ll review the memory hierarchy in the mobile systems, discuss mobile DRAM devices (like LPDD4), describe the main DRAM scaling limits, and look at what is coming next.
Memories are a key component of all computing systems. Just think that last year DRAM market has reached the value of 69B$, out of 400B$ of the whole semiconductor market. Moreover, the market feels a further boost to growth: users are eager of devices with always increasing performance which includes speed, power and capacity.
In order to meet the expected performance growth and to follow the evolving market requirements, main memory system must improve in size, technology, efficiency, cost, and management algorithms.
But mainstream memory technologies are reaching their scaling limits. Thus it’s paramount to work on different approaches: modify how the system uses main memory, change the architecture of memory devices, enable alternative technologies (emerging memories like 3D XPoint), and add functionalities to the memory systems (like error correcting codes and security primitives).
In this talk we’ll focus on mobile memories, which account for almost 50% of DRAM bits.
In particular we’ll review the memory hierarchy in the mobile systems, discuss mobile DRAM devices (like LPDD4), describe the main DRAM scaling limits, and look at what is coming next.
Short Bio
Paolo Amato received the laurea degree (cum laude) in Computer Science from the University of Milano (Italy) in 1997, and the PhD in Computer Science from the University of Milano-Bicocca in 2013. He is Distinguished Member of the Technical Staff at Micron Technologies. He joined Micron in 2010, where he investigates storage and memory architectures (based on mainstream and emerging technologies) for the next generations of mobile systems. He is an expert of statistical methods, error correcting codes and security, and of their application to mobile systems. Dr. Amato is the author of more than 50 papers published in peer-reviewed international journals and international conferences, and he filed more than 30 patents.
Emanuele Confalonieri received an M.S. degree in electronic engineering from Politecnico di Milano (Italy) in 1998. He joined STMicroelectronics in 1999 as Flash Memory Designer, later promoting to Flash Design Project Leader. He is a Senior Member of the Technical Staff and part of the Mobile Business Unit Architecture team leading the Mobile Platforms team. His responsibility spans system architectures exploration and mobile platforms prototyping. Those activities include exploring innovative memory and storage architectures based on legacy and emerging memory technologies, across the different layers of the HW/SW system stack. Mr. Confalonieri holds more than 40 patents granted, with others filed.
Marco Sforzin received the Laurea degree (cum laude) in electronic engineering from the Politecnico di Milano (Italy) in 1997. In the years 1997 and 1998 he presented many tutorials in support to the dynamical system theory and automatic control systems course at Politecnico di Milano. In 1999 he joined the Flash Memory Design team of MPG in STM, (Agrate Brianza, Italy) developing SLC NOR Flash memory devices. In 2001 he was appointed project leader of MLC NOR Flash memory prototype for wireless applications and later Design Manager in the same organization. In 2007 he joined the Advanced Architectures design team, developing Phase Change Memory devices and in 2013, the Mobile Business Unit R&D of Micron. He is currently Senior Member of Technical Staff in Micron. His expertise domains include analog design, high-speed design, full-chip mixed signals design and validation, ECC for memory and storage applications, emerging memory technologies, analytical and statistical modeling. His interests also include information theory, system theory and neural networks. Mr. Sforzin is author of 6 international papers and more than 20 patents.
Emanuele Confalonieri received an M.S. degree in electronic engineering from Politecnico di Milano (Italy) in 1998. He joined STMicroelectronics in 1999 as Flash Memory Designer, later promoting to Flash Design Project Leader. He is a Senior Member of the Technical Staff and part of the Mobile Business Unit Architecture team leading the Mobile Platforms team. His responsibility spans system architectures exploration and mobile platforms prototyping. Those activities include exploring innovative memory and storage architectures based on legacy and emerging memory technologies, across the different layers of the HW/SW system stack. Mr. Confalonieri holds more than 40 patents granted, with others filed.
Marco Sforzin received the Laurea degree (cum laude) in electronic engineering from the Politecnico di Milano (Italy) in 1997. In the years 1997 and 1998 he presented many tutorials in support to the dynamical system theory and automatic control systems course at Politecnico di Milano. In 1999 he joined the Flash Memory Design team of MPG in STM, (Agrate Brianza, Italy) developing SLC NOR Flash memory devices. In 2001 he was appointed project leader of MLC NOR Flash memory prototype for wireless applications and later Design Manager in the same organization. In 2007 he joined the Advanced Architectures design team, developing Phase Change Memory devices and in 2013, the Mobile Business Unit R&D of Micron. He is currently Senior Member of Technical Staff in Micron. His expertise domains include analog design, high-speed design, full-chip mixed signals design and validation, ECC for memory and storage applications, emerging memory technologies, analytical and statistical modeling. His interests also include information theory, system theory and neural networks. Mr. Sforzin is author of 6 international papers and more than 20 patents.
