Interconnection Network is the communication fabric that connects various components of a computer system allowing them to communicate each other with in the system. Interconnection networks can scale from on-chip networks in many-core chips or system on chip(SoC) to wired networks in HPC supercomputers or networks within datacenters. The increasing emphasis on parallelism, distributed and heterogeneous computing increased the number of components that require information exchange with each other, making the design of interconnection network critical. Among these networks, on-chip networks (also known as Network-on-Chip) allow multiple components to be present within the same silicon die, creating trade-offs between not only performance and power consumption but also includes silicon area to the equation.
Based on Prof. Tushar Krishna's course of ACACES, 2017 summer school, this talk concentrates on differences between on-chip network topologies and routing algorithms. While the main focus is the classification of on-chip networks with different aspects of performance and costs, the issues of deadlock with respect to NoCs will also be discussed briefly.
Ahmet Erdem was born on April 22nd of 1990, in Istanbul/Turkey. In 2013, He obtained his Bachelor degree in the field of Computer Science and Engineering from Sabanci University. He completed his Master's degree from Politecnico di Milano with a thesis discussing "Efficient OpenCL application autotuning for heterogeneous platforms". Currently, he is a Ph.D. student at the Dipartimento di Elettronica, Informazione e Bioingegneria of Politecnico di Milano and is collaborating with STMicroelectronics under the supervision of Prof. Cristina Silvano. His main research topics include convolutional neural network accelerators, application auto-tuning on heterogeneous platforms.