The growing race towards exascale computing is pushing the adoption of ever more heterogeneous systems into mainstream. While Graphics Processing Units are the heterogenous component of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads. However, the lack of adequate architectures, languages, runtimes, programming flexibility and, broadly speaking, proven system-level approaches in the FPGA-based supercomputing field are the most relevant limiting factors to the adoption of these devices into mainstream.
To overcome these limits we propose a CAD Framework that helps researchers and practitioners in approaching to the High Performance Computing (HPC) systems based on FPGA through a semi-automatic workflow. The Framework is capable of analyzing the user application and provide a simpler intermediate representation that can be automatic parsed and profiled. The retrieved information is used to check the applicability of different architectural templates that could augment the application performance.
This operation lightens the user's effort from the hardware-software codesign activity. Furthermore, the functions that can be implemented in hardware are automatically optimized through different techniques and the final system is provided to the user ready to be used. To validate the Frameworks and to assess its generality, we tested it against several case studies based on different applications and architectural templates. Finally the Framework is designed to be capable to integrate modules from different developers in order to stimulate external contributions and open research.