Nowadays, the interest in Deep Learning techniques has rapidly grown in many fields like image and video recognition and natural language processing.
Convolutional Neural Networks (CNNs) are the perfect example of such modern systems for their superior accuracy.
The specific computation pattern of CNNs results to be highly suitable for hardware acceleration, in fact different types of accelerators have been proposed based on GPU, Field Programmable Gate Array (FPGA) and ASIC. In particular, FPGAs represent a proper tradeoff between performance and power consumption. However, the adoption of deep learning algortihms within the embedded systems context faces significant barriers due to several aspects, from the resource requirements of these algorithms generally conflicting with the physical constraints in hardware devices, to the large design effort required to implement such approaches in hardware.
This work proposes an automated framework, called CNNECST (CNNECST is a project in the DReAMS Research Line at NECST), for the generation and synthesis of an hardware implementation of CNNs on FPGA devices given in input a high level specification of an already-trained network. Such framework offers the designer the possibility to significantly customize the characteristics of the CNN, as well as hardware implementation details. Moreover, the framework features a resource estimation model to immediately analyze the impact of the designed CNN on the reconfigurable device resources, and finally automatizes all the steps from the high level synthesis to the bitstream generation by means of Vivado Design Suite.